1. Field of the Invention
The present invention concerns a semiconductor device and a manufacturing method thereof and, in particular, it relates to a high speed and highly integrated semiconductor memory device, and a portion of a differential amplification section of a semiconductor device in which a logic circuit and a semiconductor memory device are integrated.
2. Description of the Related Arts
Dynamic random access memories (hereinafter referred to as DRAM) are semiconductor memory devices that can be mounted in various commonly used electronic equipment. Further, along with requirements for less power consumption and higher performance of equipment in recent years, there has been a strong demand for DRAM having higher performance such as a decrease in the power consumption, an increase in the operation speed and an increase in the capacity.
One of most effective means for attaining a high performance DRAM is to scale down a memory cell. The memory cell becomes small by scaling down. As a result, the length of a word line and a data line connected to a memory cell is shortened. That is, since the parasitic capacitance in the word line and the data line can be decreased, low voltage operation is possible and lower power consumption can be attained. Further, since the size of the memory cell is small, the capacity of the memory can be increased to attain higher performance of equipment. As described above, the scaling down contributes much to the increase in the performance of DRAM.
However, along with the progress of the scaling down to 65-nm node, 45-nm node, etc., various side effects have resulted in addition to enhancing the performance described above. The main side effect is an increase in the fluctuation of device characteristics caused by the scale down. The fluctuation of the device characteristics includes dispersion for the value of the threshold voltage of transistors and leakage current flowing from the transistors (deviation from average values). Since the fluctuation in the devices causes degradation of the DRAM performance, it is desirable to suppress the device fluctuation as much as possible. Particularly, a fluctuation of the differences of the threshold voltage of a pair of transistors in a sense amplifier circuit results in a noise source for the sense amplification operation that amplifies a small signal which causes reading error. That is, fluctuation of the threshold voltage of the sense amplifier gives a direct effect on the yield of chips.
Since the data line pitch of DRAM is usually narrowed along with the scaling down, it is also necessary that the layout pitch of the sense amplifiers is narrowed corresponding to the data line pitch. As a result, the channel length is shortened and the channel width is narrowed in the transistor, so that the manufacturing error of transistors constituting the sense amplifier increases. This manufacturing error increases the fluctuation of the difference of threshold voltage between the pair of transistors. Generally, the problem is referred to as an offset problem of a sense amplifier which is one of factors giving a significant effect on the access speed tRCD (RAS TO CAS DELAY) of DRAM. Further, the offset problem of the sense amplifier is described in details by Kiyoo Itoh, in “VLSI Memory Chip Design”, Springer, 2001, pp 223-230. It has been well known that a decrease of offset contributes very much to the improvement of the yield for DRAM. Accordingly, for attaining higher performance by scaling down, an extremely important technique includes decreasing the manufacturing error by the improvement in the process and taking a circuit countermeasure for suppressing the sense amplifier offset.
As an example in recent years of attempting to solve such a problem, a technique of compensating for the offset of the sense amplifier is disclosed by Sang Hoon Hong, et al., in ISSCC 2002 Digest of Technical Papers, pp 154-155. According to the method, the offset of a sense amplifier can be substantially decreased by compensating a precharge voltage of a data line using a current mirror operation amplifier. However, this method greatly increases the number of elements added to the sense amplifier, increases the area of the sense amplifier, and results in an increase of the chip size. Further, since driving control signals are also increased, a timing margin increases and the operation speed may possibly be lowered as well.
Further, a charge transfer type sense amplifier is disclosed by Jae-Yoon Simm, et al., 2003 Symposium on VLSI Circuits Digest of Technical Papers, pp 289-292. This is a method of transferring charges accumulated in a peripheral circuit such as a sense amplifier to the data line on the side of the memory cell by way of a switching transistor connected with the data line, in order to generate a high potential difference in the sense amplifier. Therefore, even in a case where the offset of the sense amplifier increases, since the higher potential difference than the offset can be applied to the sense amplifier, this amplifier is essentially stable with respect to the fluctuation and performs well in low voltage operation. However, the method also increases the number of elements to be added such as additional precharge circuitry and a rewriting switching transistor to leave a problem of resulting in which results in an increase in chip size.
Further, U.S. Pat. No. 6,392,303B2 discloses a sense amplifier circuit that includes adding two NMOS cross couples to an existent cross couple. In the added NMOS cross couples, the gate of the NMOS transistor on one side and the drain of the NMOS transistor on the other side are connected by way of a shared switch. It is described that this can attain high speed sensing operation. In this system, the on resistance of the shared switch is eliminated effectively from the NMOS cross couple and the rewriting operation speed can be increased. However, in the sensing operation upon reading, it undergoes the effect of the offset of the existent cross couple. Accordingly, in a case where the offset in the existent cross couple is large, this may possibly cause reading error.
On the other hand, Japanese Unexamined Patent Application Publication No. 2005-293759 discloses a sense amplifier circuit with a smaller number of additional devices and a decreased offset in the sense amplifier. This method solves the problem of the sense amplifier offset by adding an NMOS cross couple having a highly sensitive pre-amplifier function. Further, the number of the devices to be added is as small as two and the overhead area is also small.